Edge AI has a memory problem that DRAM pricing does not help with. A vision module running a small CNN needs fast random access for tensor workloads plus a fat, cheap buffer for camera frames — but dedicated mobile DRAM is overpriced, over-complex to lay out, and overkill on bandwidth. PSRAM in the Xccela camp sits precisely in that gap, and the APS256XXN-OB9-BG from AP Memory is its 256 Mb workhorse.
The short answer
The APS256XXN-OB9-BG is the memory to pick when your edge AI board needs hundreds of megabits of working memory, 500–1000 MB/s of bandwidth, and a solution that lays out like flash rather than like DRAM. One 1.8 V supply, no controller-side refresh management burden, no fly-by termination.
Verified key parameters
From the AP Memory datasheet (Rev 1.2, Jan 2025):
| Parameter | Value | Condition / Note |
|---|---|---|
| Density | 256 Mb (32 MB) | X8 default, X16 configurable |
| Supply | VDD and VDDQ 1.62 – 1.98 V | Single 1.8 V rail |
| Interface | OPI (Octal) / HPI / Xccela mode | Register-configurable |
| Clock rate | up to 250 MHz | Double-data-rate |
| Throughput X8 | 500 MB/s read/write | Two bytes per clock |
| Throughput X16 | 1000 MB/s read/write | Two words per clock |
| Organisation X8 | 32M × 8 | 2048 bytes per page |
| Organisation X16 | 16M × 16 | 1024 words per page |
Why PSRAM rather than DRAM or SRAM at the edge
It behaves like SRAM to the host. PSRAM hides its DRAM core behind a self-managed refresh controller. Your SoC talks to it over an octal SPI-class bus with standard read and register commands — no row/column addressing discipline, no DQS strobes, no termination scheme. For a two-engineer firmware team shipping a camera edge box, that alone removes a month of signal-integrity bring-up.
Bandwidth that matches the workload. A 250 MHz double-data-rate octal bus delivers 500 MB/s in X8. Typical small-CNN workloads — a 1080p frame buffer plus feature-map ping-pong — land comfortably inside that envelope. If the design moves to 16-bit bus mode, 1000 MB/s covers stereo vision and multi-stream cases.
Power profile fits battery and always-on boxes. A single 1.62–1.98 V rail for both core and IO keeps the power tree trivial. Compare with DDR3L's VDD/VDDQ pairing plus termination power, and the difference in an always-listening camera node is measurable in battery weeks.
Where it sits in an edge AI memory hierarchy
A typical vision-edge architecture looks like this:
- Code and model storage — SPI NOR flash (e.g. PY25Q series)
- Working memory for tensors and frame buffers — APS256XXN Xccela PSRAM
- Optional bulk cache — larger PSRAM (APS512XXN) or SPI NAND
The APS256XXN-OB9-BG's 32 MB covers the common case: one to two 1080p luma/chroma frame buffers plus several megabytes of feature-map workspace. Designs that need more headroom step to the 512 Mb APS512XXN on the same bus protocol.
Layout and integration notes
- Bus width is register-configurable — X8 is the default at power-up, X16 is a mode-register setting, so one PCB supports both configurations
- Xccela mode compatibility — hosts with Xccela-compliant memory controllers attach without protocol translation
- Page size discipline — 2048-byte pages in X8 mean the memory controller's burst policy should respect page boundaries for best efficiency
- Package — standard BGA suitable for standard reflow; no PoP stacking concerns like mobile DRAM
Frequently asked questions
Is Xccela PSRAM the same thing as HyperRAM?
No. They are both PSRAM families with high-bandwidth octal buses, but the protocols differ — Xccela (OPI/HPI) and HyperBus are distinct interfaces. The APS256XXN-OB9-BG speaks OPI/HPI/Xccela; a HyperRAM-only host cannot address it. Match the memory to your SoC's controller.
How much bandwidth do I actually get in X8 mode?
250 MHz clock, double-data-rate, two bytes per clock — 500 MB/s sustained read/write throughput. X16 mode doubles that to 1000 MB/s.
Can it replace DDR in a design with a memory-controller-constrained SoC?
Only if the SoC has an OPI/Xccela PSRAM or octal-SPI memory controller. The point of this part is exactly that: SoCs without a full DDR subsystem can still get hundreds of MB/s through a low-pin-count interface.
What is the difference between APS256XXN and APS512XXN?
Density — 256 Mb versus 512 Mb — on the same bus protocol and voltage class. The 512 Mb part doubles the working window for heavier model workloads or multi-stream video.
Sourcing note
The APS256XXN-OB9-BG is available through Mandu with the full AP Memory datasheet package. Send your SoC interface, density requirement and volume for pricing and availability, including X16-configured variants.