Every embedded board needs a place for the firmware to live, and for a huge class of designs the answer has been the same for a decade: 128 Mbit SPI NOR in an SOP-8. The P25Q128L from PUYA (Puya) plays exactly that role in the 1.8 V world — a low-voltage 128 Mbit SPI NOR flash that drops into the industry-standard command set, with the endurance and retention figures that make code storage boring in the best way.
The short answer
If your host runs at 1.8 V IO and needs 16 MB of execute-in-place or shadowed code storage with a standard SPI NOR command interface, the P25Q128L is the straightforward pick — mainstream density, mainstream package, supply-chain-friendly pricing.
Verified device identity
From the PUYA P25Q128L datasheet V2.0:
| Attribute | Value |
|---|---|
| Density | 128 Mbit (16 MB) |
| Interface | SPI (serial peripheral interface) |
| Supply class | 1.8 V low-voltage family |
| Package family | SOP-8 and compatible variants |
| Command set | Industry-standard SPI NOR |
The P25Q128L sits in PUYA's low-voltage (L-suffix) family alongside the 3.3 V P25Q128H-class parts; the L designation targets hosts with 1.8 V flash interfaces — battery devices, modern SoCs with 1.8 V memory banks, and designs running QSPI at the lower rail for power reasons.
Why 128 Mbit keeps being the answer
It matches the bootloader-plus-application reality. A Cortex-M-class MCU with XIP (execute-in-place) through its QSPI controller consumes flash at a steady rate: bootloader, application, assets, OTA staging. 16 MB covers the comfortable upper range of that pattern — enough for an RTOS, a GUI asset pack, an ML model or two, and double-buffered OTA.
SOP-8 is a solved problem. Layout, reflow, programming fixtures, second sources, footprint conventions — the 208-mil SOP-8 SPI NOR footprint is the most standardised package in memory. A design that uses it keeps every sourcing option open.
The dual-bank OTA pattern. 16 MB lets a design keep two complete firmware images resident — the running one and the staged one. Smaller densities force OTA dance steps (external staging, compression, partial updates) that 16 MB simply avoids.
Where the P25Q128L fits in a design
Typical hosts and roles:
- Wi-Fi and BLE SoCs — 1.8 V QSPI XIP code storage
- Linux-class small SoCs — bootloader and kernel storage
- MCU + display systems — GUI asset storage
- Edge AI sensor nodes — model weight storage alongside PSRAM working memory
In the memory tier: P25Q128L for code and assets, PUYA or CONNTEK PSRAM (APS/CSS series) for working memory, EEPROM for calibration data.
Selection notes within the family
- Voltage letter — H-suffix for 3.3 V hosts, L-suffix for 1.8 V hosts. Match the host's memory rail before anything else.
- Package suffix — SOP-8 is the volume default; check the ordering code for WSON/USON options if your assembly is height-constrained.
- Speed class — QSPI hosts benefit from fast-read and dual/quad commands; confirm the specific speed grade in the ordering information when the host runs XIP at high clock rates.
Reliability expectations for code storage
Code storage flash lives an easy life compared with data-logging flash: firmware writes happen at OTA cadence — dozens to hundreds of cycles over the product's life, not millions. SPI NOR endurance and retention specs cover this workload with enormous margin; the practical reliability drivers are proper power-ramp handling (the host's hold/reset discipline) and legitimate sourcing. We supply lot traceability with every shipment precisely so the second point stays boring too.
Frequently asked questions
Is the P25Q128L compatible with standard SPI NOR command sets?
Yes. It implements the industry-standard SPI NOR command interface that hosts and programmer fixtures already support — treat it as a mainstream-density drop-in within the 1.8 V class.
P25Q128L versus P25Q128H — which one for my board?
The rail voltage decides. Host memory interface at 1.8 V — the L part. At 3.3 V — the H part. Mixing them burns level shifters or worse; check the SoC's flash rail first.
Can I execute code directly from it (XIP)?
Yes, provided the host SoC has a QSPI XIP memory controller — the standard pattern for Wi-Fi SoCs and application MCUs with flash-on-bus architectures.
What about OTA on 16 MB?
Comfortable. The typical pattern keeps the active image in one bank and stages the update in the other, with the bootloader switching on validated boot. 16 MB accommodates the doubled image for firmware sizes up to several megabytes with room for assets.
Sourcing note
The P25Q128L ships through Mandu with the PUYA datasheet, ordering-code guide and lot traceability. Send your host platform, package and annual volume for pricing and lead time.