Ask an embedded designer what working memory costs in pins and they will describe the classic dilemma: parallel SRAM eats 40 pins and 8 square centimetres; SDRAM wants a controller, a clock tree and a routing discipline the MCU may not even have. The QSPI PSRAM class — and the CSS6404L from Cascadeteq (Kaixin) in particular — exists to break that dilemma: DRAM-density working memory on a ten-signal bus that any QSPI controller can drive.
The short answer
The CSS6404L is the working-memory pick for 3.3 V MCU designs that need 8 MB of RAM, have a QSPI controller and a small board, and do not have (or do not want) a full SDRAM subsystem.
Verified device identity
From the Cascadeteq CSS6404L datasheet V1.0 (Dec 2022):
| Attribute | Value |
|---|---|
| Density | 64 Mbit (8 MB) |
| Interface | Quad-SPI (QSPI) |
| Supply class | 3.3 V |
| Memory type | Pseudo-SRAM (self-managed DRAM core) |
| Vendor | Cascadeteq Inc |
The CSS6404L belongs to the 3.3 V L-family; the S-family variants (CSS6404S) cover the 1.8 V class, so one design pattern serves both voltage worlds.
The PSRAM value proposition, concretely
Pin count. Parallel SRAM at 8 MB class: address + data + control in the dozens of pins. CSS6404L: QSPI's six to ten signals (CLK, CS, IO0–3 or IO0–7 on octal parts, plus optional DQS on faster classes). The difference is often the difference between a 64-pin and a 100-pin MCU — or between a two-layer and a four-layer board.
Controller burden. The DRAM core inside refreshes itself. The host sees standard QSPI read/write and register commands. No refresh interrupt, no row-policy tuning, no init sequence — firmware treats it like slow-but-roomy SRAM.
Cost per bit. Against true SRAM, PSRAM's DRAM core wins on density economics by a wide margin at 8 MB class — the reason SRAM vendors have largely retreated above 4 Mb.
Where the 8 MB / QSPI point lands
Real workloads that fit the CSS6404L:
- Voice front-ends — audio frame buffering, echo cancellation state, keyword-spotting models
- GUI panels — one full-frame buffer at 320×240×16bpp (150 KB) with double buffering and widget caching to spare
- Data loggers — high-rate sensor buffering before batched writes to NOR flash
- Network nodes — packet buffers and TLS session state on 3.3 V Wi-Fi/BLE gateways
And the memory tier around it: NOR flash (P25Q/CMS25Q class) for code, CSS6404L for working memory, EEPROM for calibration and counters.
QSPI PSRAM versus the alternatives
| Option | Density | Pins | Host controller needed | Typical use |
|---|---|---|---|---|
| Parallel SRAM | ≤16 Mb | 40+ | None | Legacy, deterministic access |
| SDRAM (SDR/DDR) | 512 Mb–8 Gb | 30–78 | SDRAM controller | Linux-class hosts |
| QSPI PSRAM (CSS6404L) | 64 Mb | ~10 | QSPI | MCU-class 8 MB working memory |
| OPI/Xccela PSRAM | 256–512 Mb | ~12 | OPI/Xccela controller | High-bandwidth edge AI |
The ladder is coherent: QSPI PSRAM at 8 MB for MCU designs, OPI PSRAM at 32–64 MB for bandwidth-hungry edge AI, SDRAM above that. The CSS6404L owns the first rung.
Integration notes
- Check your QSPI controller's PSRAM support — most modern MCUs (and many Wi-Fi SoCs) have memory-mapped QSPI modes that transparently XIP/cache over PSRAM; confirm the command-set match in the datasheet
- 3.3 V rail — clean single-supply; the S-suffix parts move to 1.8 V if your platform is a low-voltage design
- Clock discipline — QSPI PSRAM timing is forgiving at typical 80–104 MHz controller clocks; follow the datasheet's AC table for the speed grade in your ordering code
Frequently asked questions
Can I execute code from the CSS6404L?
PSRAM is RAM — code can run from it, but the typical architecture executes from NOR flash (XIP) and uses the PSRAM for data, heap and buffers. Memory-mapped QSPI controllers can cache PSRAM regions transparently either way.
CSS6404L versus CSS6404S — same die, different rail?
The L-family is the 3.3 V class, the S-family the 1.8 V class. Functionally the design pattern is identical; pick by your board's memory rail.
How does it compare with the APS6404-class 3.3 V QSPI PSRAMs?
Same interface class and density point — 64 Mb QSPI PSRAM at 3.3 V. Practical selection comes down to package options, speed grades and supply terms; we quote both families and hold the datasheet sets for a direct comparison on your platform.
Is 8 MB enough for a GUI frame buffer?
Comfortably. A 480×272 16-bit frame is 255 KB; double buffering plus widget cache stays under 1 MB — the CSS6404L's 8 MB leaves most of the window for application state.
Sourcing note
The CSS6404L family ships through Mandu with the Cascadeteq datasheet set. Send your MCU platform, rail voltage and annual volume for pricing, samples and the L/S variant comparison.