An IP camera board asks its boot flash to do three jobs at once. It holds the bootloader the SoC fetches at power-up, it stores the settings and calibration data the firmware rewrites in the field, and it often holds a static logo or voice prompt bank. The W25X20CLUXIG covers all three on a small camera board. It clears every common constraint these boards set: a single 2.3 to 3.6 V rail, an outdoor-grade temperature range, and a pad package small enough to hide under the lens assembly. The 104 MHz SPI clock with dual-output read keeps early boot code streaming fast enough for XIP.
The call is easy to state up front. If your firmware image fits in roughly 200 KB and you rewrite settings a few times a day rather than a few thousand, this part is a good fit and you should stop reading reviews and start a layout. If the image needs more room, the same die exists as a 4 Mbit W25X40CL in the same pad package, and the swap costs nothing on the PCB. This article walks the whole build stage by stage, because the part touches a different decision at each one.
What the board forces on the part
Start with what the board forces on the memory, not with the memory itself. An IP camera runs from PoE or a wall adapter, so the flash sits on a main rail that is almost always 3.3 V. The W25X20CL family accepts 2.3 to 3.6 V on a single supply (p. 4), which means the part survives rail sag during motor or IR-cut filter events without a local regulator.
Power matters just as much. The datasheet rates read current at 6 mA typical and 12 mA maximum when the clock runs at 104 MHz (p. 38). Standby sits at 10 µA typical, and a deep power-down command drops supply current to 1 µA typical (p. 38). For a camera that spends most of its life recording rather than reading firmware, the standby and power-down numbers matter more than the active ones.
The next envelope item is temperature. Outdoor housings in direct sun routinely cook the electronics past the ambient air temperature, so the industrial rating of −40 to +85 °C (p. 36) is a real limit, not a formality. Endurance is the last item, and this is where small-sector flash earns its place: the array divides into 4 KB sectors, and the datasheet rates the part at more than 100,000 erase/write cycles with more than 20-year data retention (p. 4). A settings sector rewritten a few times a day will outlive the camera by a wide margin.
| Parameter | W25X20CLUXIG value | Datasheet |
|---|---|---|
| Density | 2 Mbit, 1,024 pages of 256 bytes | p. 4 |
| Supply range | 2.3 to 3.6 V single rail | p. 4 |
| Clock, all instructions except 03h read | 104 MHz at 2.7 to 3.6 V, 80 MHz at 2.3 to 2.7 V | p. 40 |
| 03h Read Data clock | 50 MHz at 2.7 to 3.6 V | p. 40 |
| Dual Output read | 208 MHz equivalent transfer | p. 4 |
| Active read current at 104 MHz | 6 mA typ, 12 mA max | p. 38 |
| Standby current | 10 µA typ, 50 µA max | p. 38 |
| Power-down current | 1 µA typ, 5 µA max | p. 38 |
| Page program time | 0.4 ms typ, 0.8 ms max | p. 41 |
| Sector erase time (4 KB) | 30 ms typ, 300 ms max | p. 41 |
| Operating temperature | −40 to +85 °C | p. 36 |
| ESD, human body model | 2000 V | p. 36 |
| Package | 8-pad USON, two by three millimeter body | p. 49 |
One envelope trap deserves its own paragraph. The 2 Mbit density is only 256 KB, and boot code has a way of growing. Set a hard rule at the start of the project: the bootloader plus recovery image must stay under half the array, because the other half is where settings, calibration and the logo bank live. Teams that skip this rule end up migrating density in the middle of certification, and migration is a re-test, not a recompile.
Reading the datasheet with the BOM open
With the envelope fixed, the datasheet does the picking. The ordering code decodes cleanly. W marks Winbond, 25X marks the SpiFlash family with 4 KB sectors and dual SPI, 20C is the 2 Mbit density, and L is the 2.3 to 3.6 V operating range. UX is the 8-pad USON in a two by three millimeter body, I is the industrial temperature range, and G is the green, halogen-free package (p. 48). The exact part number to freeze into the BOM is therefore W25X20CLUXIG, and there is no suffix ambiguity beyond the packing code you request.
Two details in the datasheet decide whether early boot is fast enough. First, the clock ceiling depends on the rail: every instruction except the legacy 03h read runs at 104 MHz when VCC is in the 2.7 to 3.6 V window, and drops to 80 MHz between 2.3 and 2.7 V (p. 40). On a 3.3 V rail you get the full rate. Second, the Fast Read Dual Output instruction doubles the effective transfer to 208 MHz equivalent, and the continuous read mode cuts instruction overhead to as few as 16 clocks per access, which is what makes true execute-in-place boot practical (p. 4).
The package choice is where cameras differ from other products. The UX package is an 8-pad USON with a two by three millimeter footprint, and the datasheet notes it carries a special abbreviated top marking of 2Hxxx or 0Gxxxx because the standard marking does not fit (p. 49). If your contract manufacturer hand-solders engineering samples or your production test fixture probes packages rather than pads, the same die comes as W25X20CLSNIG in an 8-pin SOIC 150-mil body, which is the pick for bring-up boards. The density ladder in the same family gives clean escape routes in both directions. W25X10CLSNIG halves the array to 1 Mbit with 512 pages. W25X40CLSNIG or W25X40CLUXIG doubles it to 4 Mbit with 2,048 pages. Both keep the same 256-byte page size and 4 KB sector grid (p. 4 of their own datasheets).
Bring the JEDEC ID into your production test plan at this stage, not later. The part answers the 9Fh instruction with the standard manufacturer and device identification and also carries a 64-bit unique serial number (p. 4), which is enough to distinguish genuine parts from remarked ones on the production line without opening the package.
Traps that only show up on the bench
The power-up sequence is the first trap, and the datasheet is explicit about it. After VCC rises, /CS must track the supply and the device ignores instructions until it has settled: the part requires 10 µs from stable VCC before /CS may go low, and 5 ms before the first write instruction is accepted (p. 37). Below about 1.0 to 2.0 V the write-inhibit threshold keeps programming disabled (p. 37), which protects the array during a brownout, but only if your SoC does not hammer the bus with commands during the ramp. Put a pull-up on /CS sized so it tracks VCC, exactly as the pin description recommends (p. 6), and gate your bootloader's first flash access on the 5 ms timer rather than on the reset release alone.
The second trap is the HOLD and /WP pin set. On a camera board the SPI bus is often shared with a sensor bridge or an audio codec, and the /HOLD input lets the flash pause while another device uses the bus (p. 6). Leaving /HOLD floating produces intermittent read corruption that looks like firmware bugs; tie it through the appropriate pull-up and reserve it for the shared-bus case. Likewise /WP, used together with the status register's block-protect bits, can hardware-protect the bootloader region (p. 6), which is the cheapest insurance available against a runaway write corrupting the image the camera needs to boot.
The third trap is timing margin rather than protective pins. Keep the clock within the AC limits, where clock high plus clock low must fit inside one clock period. The /CS deselect time between array reads is 50 ns (p. 40). Input capacitance is 6 pF maximum (p. 38), so a long shared trace with two other loads eats that budget quickly. Bring-up teams that see reads fail only above 80 MHz almost always find a trace-length or pull-up problem rather than a bad part.
Sign-offs before the production run
Production cares about three things: programming time, marking, and packing. Page programming takes 0.4 ms typical and 0.8 ms maximum, a 4 KB sector erases in 30 ms typical, and a full chip erase finishes in 0.5 to 2 s (p. 41). An in-circuit test station can therefore wipe and rewrite the whole array inside a normal test slot. The green package option is lead-free, RoHS compliant and halogen-free (p. 48), which keeps export filings simple.
Marking is the detail that trips audits. The USON package carries the abbreviated 2Hxxx or 0Gxxxx top marking instead of the part number (p. 49), so incoming inspection must verify through the JEDEC ID command rather than by reading the package. Ordering is flexible on packing: standard bulk shipments come in tubes, and tape and reel or tray packing is specified when ordering (p. 48), so tell your distributor the feeder type your line expects before the purchase order goes out.
Lifecycle is worth one paragraph before the design freezes. This datasheet is Revision F, published in 2015, and the SpiFlash catalog behind it spans densities far beyond this part, which is the usual shape of a long-running, long-term product line. Ask for the PCN and EOL policy in writing when you qualify the part, so the camera program is covered across its service life.
None of this changes firmware, and that is the quiet advantage of staying inside the W25X20CL family. W25X20CLSNIG and W25X40CLUXIG use the same instruction set, the same status register layout and the same protection scheme. A density or package change is a line-item edit, not a driver project.
Frequently asked questions
How fast can I get engineering samples for a camera prototype?
Tubes of standard parts are the default bulk shipment, and tape and reel or tray packing is available on request (p. 48). For a camera prototype you only need a tube; send us your target quantity and schedule and we will confirm stock and ship a reel if your pick-and-place run starts early.
What layout mistakes show up most often on this part?
Three, in order of frequency: a floating /HOLD pin on a shared bus, a /CS pull-up that does not track VCC during the power ramp, and ignoring the 5 ms delay before the first write instruction (p. 37). All three produce symptoms that look like firmware faults, and all three are checked with a scope in one afternoon.
Will parts bought across different build lots behave identically in production?
The instruction set, status register and timing tables are fixed across the family, and the 9Fh JEDEC ID plus the 64-bit unique serial number (p. 4) give the production line a per-unit identity check. Verify by command response rather than by package marking, because the USON body carries only the abbreviated code (p. 49).
What if 2 Mbit turns out to be too tight?
Move inside the family first. W25X40CLSNIG or W25X40CLUXIG doubles the array to 4 Mbit with no PCB change for the UX option. If the project later grows into quad I/O or a 1.8 V rail, there are pin-compatible alternatives at other vendors. P25Q128L is a 128 Mbit part on a 1.65 to 2.00 V supply. BY25Q16ES is a 16 Mbit quad part with a 0.16 ms typical page program. CMS25Q64A is a 64 Mbit quad part that idles at 0.7 µA in power-down. Each of those is a different footprint and driver effort, so treat them as a redesign path, not a drop-in swap.
Sourcing note
The exact part number for camera production is W25X20CLUXIG, industrial temperature, green package, in the two by three millimeter USON pad format. W25X20CLSNIG covers the same die in SOIC for low-volume builds. Contact us with your annual volume, target rail voltage and packing preference, and we will send a quotation with lead times for both tube and tape-and-reel options.