A pack comes back from a service swap with a hole in its history. The entries written after the last quick reconnect are gone, and the log pointer sits on a record older than the ones that vanished. Twice the service notes mention the BMS went silent on the two-wire bus until the pack sat disconnected overnight. On the bench the board is perfect: every byte reads back, every checksum matches, a full charge and discharge passes.
That combination points away from firmware and toward a power window the EEPROM owns. The datasheet is blunt about it. For the device to re-initialize on power-up, VCC must fall below 0.7 V and stay there for at least 300 µs, and once the rail comes back cleanly the part needs 70 µs before it accepts its first command (p. 8). A contactor that recloses in a few hundred microseconds, or a logic rail held up by bulk capacitance while the pack management decides, never gives the device that window. The EEPROM keeps whatever internal state it had, and the host controller, which rebooted long before, talks to a partner that never did.
The P24C256-UNH-MIR is the right answer for pack-level logging at this density, and it goes marginal only where firmware treats an EEPROM write like a register store. It is a 256 Kbit I2C EEPROM with 64-byte pages, running from 1.7 to 5.5 V at 400 kHz or 1 MHz, with a self-timed write cycle of 5 ms, endurance of 1,000,000 cycles, data retention of 100 years and 6 kV of HBM robustness (p. 1, p. 6). The order code lands it in the 2.00 mm × 3.00 mm UDFN8 body on a 0.50 mm pitch (p. 21). None of that fixes a dropped write by itself. What fixes it is firmware that respects the windows this article walks through.
What the failure looks like in the field
The signature is absence, not corruption. A checksum catches damaged data; it says nothing about a record that was never written. The pack looks healthy, the log looks self-consistent, and the newest entries after a specific moment simply do not exist. The moment is almost always a fast reconnect: a charger hot-plug, a protection FET that trips and recovers, a contactor that chatters under load.
Three details separate this from a firmware bug. First, the loss clusters at reconnects, not at random times, and it happens on packs whose logs write every few seconds rather than every minute. Second, the pointer is consistent with the surviving data, which means the write sequence started but the record never landed. Third, the occasional bus hang. SDA is an open-drain line, and a slave stuck mid-transaction holds it low, so no stop condition can be generated and the bus stays dead until the host clocks the slave out or removes power (p. 2). A bench supply cannot reproduce any of this, because a bench collapses the rail cleanly below the power-down threshold and keeps it there. Real packs bounce.
Weather matters less than connect-disconnect rhythm. A swap-station fleet sees the dropout weekly; a pack that lives in one charger for months may never show it. That pattern points at the power-up contract rather than cell chemistry.
Why it happens at the silicon level
The device has a built-in power-on reset circuit that initializes the EEPROM during power-on, and the datasheet defines exactly what a valid power cycle means. VCC must drop below 0.7 V, the VPWD threshold, and remain there for at least 300 µs, the tPWD window, before power returns; rise time must land between 1 and 500000 µs/V (p. 8). A reclose that dips the rail to a volt and recovers in under a millisecond satisfies none of it. The part never re-initializes, and whatever transaction was in flight when the rail dipped stays half-digested in the device state machine.
Writes make this worse because a write is a blackout. After the stop condition the part starts an internally timed cycle and disables all inputs until it finishes (p. 12), and the cycle is 5 ms maximum (p. 6). The only honest completion signal is acknowledge polling: send a start condition plus the device address, and the part answers only once the internal cycle has ended (p. 13). Firmware that waits a fixed delay shorter than the worst case issues its next command into silence and leaves the record unwritten.
The page is the unit of damage. A page write covers 64 bytes (p. 1); the low address bits increment within the row, and more than 64 data words roll over to the start of the same page and overwrite what is already there (p. 12). A log record that straddles a page boundary is two writes with a second exposure window between them, and a record longer than one page silently clobbers its own header.
Two pins finish the story. E0, E1 and E2 set the slave address and float low internally when left open, and WCB, the write-control pin, also floats low, which permits writes; tying WCB to VCC blocks all writes to the array (p. 2, p. 3). A board that left WCB unconnected to save a resistor has no hardware write protection at all, which turns every brownout glitch into a potential write.
Recovery, when the device does come up in a bad state, is the soft reset sequence: a start condition, nine clock cycles, then another start followed by a stop (p. 10). Few firmware stacks issue it.
The numbers that fix it
| Item | Value from the datasheet | Source |
|---|---|---|
| Supply voltage | 1.7 to 5.5 V across the speed range | p. 5 |
| Bus clock | 400 kHz and 1 MHz from 1.7 V | p. 1 |
| Standby current | 1.0 µA maximum at 3.3 V and 85 °C | p. 5 |
| Read current | 0.2 mA typical, 0.4 mA maximum at 5.5 V, 400 kHz | p. 5 |
| Write current | 0.8 mA typical, 1.6 mA maximum at 5.5 V, 400 kHz | p. 5 |
| Write cycle time | 5 ms maximum, self-timed | p. 6 |
| Endurance | 1,000,000 write cycles at 25 °C and 3.3 V, page mode | p. 6 |
| Data retention | 100 years at 55 °C | p. 6 |
| Power-down threshold | below 0.7 V held for at least 300 µs | p. 8 |
| Restart latency | 70 µs from a valid power-up to first command | p. 8 |
| ESD and latch-up | 6 kV HBM, 200 mA latch-up current at 25 °C | p. 1 |
| Package | UDFN8, 2.00 mm × 3.00 mm body, 0.50 mm pitch | p. 21 |
The first pair to design around is 0.7 V and 300 µs. The pack rail must either stay above the EEPROM minimum operating voltage long enough to survive a whole 5 ms write, or collapse decisively below 0.7 V and stay there past 300 µs so the device re-initializes. The middle ground, a slow sag that dips and recovers, is the one that loses records, and the one a bench never emulates. Bulk capacitance buys the first behavior; a bleed path on the logic rail buys the second.
The second pair is 5 ms and the 64-byte page. One record, one page write, one exposure window. A rotating log that appends a short fixed-size record per event and never crosses a page boundary has a worst case of exactly one interrupted write. Acknowledge polling turns even that into a detectable event instead of a silent one.
The third is the temperature grade hiding in the order code. Decoded, P24C256-UNH-MIR reads as the Puya I2C EEPROM family, 256 Kbit, UDFN8 package, H plating with RoHS compliance and halogen-free and antimony-free build. M is the voltage class from 1.7 to 5.5 V, I the grade from -40 to +85 °C, R shipping on tape and reel (p. 16). The I grade is the right fit for a pack mounted away from heat sources; K and E grades extend to +105 and +125 °C for packs that sit near an inverter. The grade letter follows the mounting position, not the design.
The family around it gives an upgrade path in both directions without leaving the footprint or the driver. P24C64C is the 64 Kbit sibling with 32-byte pages, a 128-bit serial number feature and the widest body list of the family, including SOT23-5 and WLCSP4, and the same 1 million write cycles and 100 years of retention. P24CM01B quadruples the density to 1024 Kbit with 256-byte pages, reads at 0.4 mA typical and fits a 3 mm DFN, though its two address pins mean four devices on a bus instead of eight. At the small end, P24C02A holds 2 Kbit in 8-byte pages with a 4 kV HBM rating, and the suffix walks through five bodies. P24C02A-DPH-MER is the PDIP8 build with the E grade that reaches +125 °C. P24C02A-MSH-MKR is MSOP8, P24C02A-SSH-MKR is SOP8, P24C02A-STH-MKR is SOT23-5 and P24C02A-TOH-MKR is TSOT23-5, those last four in the K grade to +105 °C. A pack platform can standardize on one driver and scale density per variant.
Verification you can run before the next build
- Scope the logic rail through a real contactor reclose and measure how long it spends between the EEPROM minimum operating voltage and 0.7 V. That dwell time is your dropout exposure.
- Command contactor chatter with dwell times just under 300 µs and run a few hundred reconnect cycles against a pack that logs every second. If the log loses records, the rail is in the dead zone; if not, the firmware contract below is holding.
- Issue the soft reset sequence after every power event that fails the power-down test: start, nine clocks, start, stop (p. 10). It costs nothing and clears a slave stuck mid-transaction.
- Replace fixed write delays with acknowledge polling and a timeout. The part answers only after the internal write cycle ends (p. 13), so a missing acknowledge is a completion signal, not a bus fault.
- Keep every log record inside one 64-byte page and alternate between two slots with a sequence number. Recovery becomes a comparison, never a repair (p. 12).
- Write the pack identity into the Identification Page, 64 bytes writable once and then permanently locked read-only (p. 13), and try the lock exactly once, on a scrapped unit, because the lock has no undo.
Frequently asked questions
Does moving to this part require hardware changes?
Electrically, no. It is a two-wire I2C device across 1.7 to 5.5 V, the only external component the bus needs is the SDA pull-up, and the UDFN8 body keeps the footprint small.
The work is firmware: acknowledge polling instead of fixed delays, records that fit one page, and the soft reset sequence after dirty power events (p. 10).
Which other devices fail this same way?
Any EEPROM with a self-timed write cycle and a power-on reset window, which is the whole class. P24C64C and P24CM01B specify the same 5 ms write behavior, so a torn write leaves a stale record there too. The difference is how much damage one interrupted cycle can do, and that tracks the page size.
How do I verify quickly?
Two tests cover both halves. A rail-dwell test with the contactor, as above, proves the power-up contract. Then a scripted burst of writes cut at random offsets by a MOSFET in the supply path proves the record format survives a torn write. One afternoon, a scope, a spare pack.
What does it cost against the part we use now?
The comparison that matters is warranty returns against a log nobody can trust. Parts in this class sit at commodity pricing, and the 1,000,000-cycle endurance with 100-year retention (p. 6) means the write budget is not the constraint. Ask us to quote against your current suffix and volume.
Sourcing note
The P24C256-UNH-MIR ships on tape and reel in the UDFN8 body, with the K and E temperature grades and the SOP8, TSSOP8 and DFN8 bodies available under adjacent order codes (p. 16). For programs that run several years, ask us to confirm the long-term availability and any PCN or EOL plans for the exact suffix before freezing the BOM.
Tell us the pack platform, the mounting position and the annual volume, and we will quote current stock and lead time, including the 64 Kbit and 1 Mbit siblings for a density ladder.