MX30UF4G18AC-XKI for a Data Logger When Energy and Retention Decide

A data logger is a budget exercise before it is a memory problem. It runs a sampling loop, keeps weeks of readings, and does both on whatever a primary cell or a small solar panel can spare. Every milliamp-hour spent talking to the flash is a milliamp-hour not spent on the sensor.

This build uses the Macronix MX30UF4G18AC-XKI, a 4 Gbit SLC NAND flash in a 63-ball VFBGA. It is a 1.8 V part with a x8 bus, an ONFI 1.0 interface and a 4-bit ECC requirement per 528 bytes of page data. For a logger that writes a page every few minutes and sleeps between writes, it clears the energy and capacity constraints with room to spare.

Two constraints are where the decision gets made. The temperature ceiling is plus 85 °C, so a sealed enclosure in direct summer sun is the thing to measure, not the air temperature on the site sheet. And the host has to deliver 4-bit ECC per 528-byte sector, because the datasheet treats that as a condition of the endurance and retention numbers. A logger built on an MCU with a 1-bit ECC unit is the wrong host for this part.

The constraints that actually decide this

Four constraints do the filtering, and only four.

Energy per stored byte. The logger wakes on a timer, takes a reading, writes it, and goes back to sleep. The cost that matters is not standby current but program time multiplied by program current. A part that needs a millisecond of busy time per write costs more than a part that needs a third of that.

Retention in a box that heats up. Field loggers are expected to come back with readable data after a decade. Retention is quoted at a temperature, and the part has to be credible at the top of the box's real range.

Board area. A logger board is small, often potted, and always tight. A 48-pin TSOP and a 63-ball VFBGA are not interchangeable in a mechanical sense even when the silicon is identical.

Host capability. SLC NAND is not a file system. It ships with bad blocks, it needs ECC, and it needs the host to keep a bad block table.

Here is the envelope, from the datasheet.

Four rows carry the decision: the 1.7 – 1.95 V window, the plus 85 °C ceiling, the 320 µs program time and the 4-bit ECC condition attached to the endurance figure.

Mapping each constraint to a datasheet number

Energy. The read path is cheap: 25 µs from array to register, then 25 ns per sequential byte (p. 6). The write path is where the budget goes. Page program takes 320 µs typical and 600 µs maximum at 23 mA typical program current (p. 69, p. 70). Against that, standby is 10 µA typical and 50 µA maximum (p. 69). That ratio is the whole argument for a page-at-a-time logger that sleeps between writes: firmware that wakes to write a single byte never reaches standby, and the standby figure stops mattering.

One more energy number catches people out. Staggered power-up current is 30 mA maximum with a 1 ms rise time and 0.1 µF of line capacitance (p. 69). A logger that power-gates the flash to save standby current pays that inrush on every wake, so the sleep strategy and the power switch have to be decided together.

Retention and wear. The endurance row reads 100K cycles, and the parenthetical matters more than the number: with 4-bit ECC per 512 + 16 byte (p. 6). Data retention is 10 years (p. 6). Both are conditional on the host doing its part. The array holds 4096 blocks of 64 pages, and a logger appending sequentially spreads writes so thin that cycle count never becomes the limit.

Temperature. The operating range is -40 to +85 °C, from Table 10 on p. 69. There is no wider grade in this datasheet. That is a boundary to design against, and the sensor to trust is the one bonded to the flash package.

Area and mechanical. The 63-ball VFBGA measures 9 mm by 11 mm with a 1.0 mm height, 0.8 mm ball pitch and 0.45 mm ball diameter (p. 8, p. 83). The same silicon is offered in a 48-pin TSOP measuring 12 mm by 20 mm (p. 6). Both are RoHS compliant and halogen-free.

Bad blocks. The guaranteed minimum is 4016 valid blocks out of 4096 (p. 78). That is the number for the capacity budget, not the marketing density. Block 0 is guaranteed good for at least 1000 program and erase cycles, which is what makes it usable as the place to park a bad block table.

The family around it. Density and rail are where the alternatives differ, and they differ in ways that change the driver.

The MX30LF1G18AC is the 3 V sibling at 1 Gbit, running from 2.7 to 3.6 V with the same 2048 + 64 byte page and the same 4-bit ECC per 512 + 16 byte. Its standby current is 80 µA maximum rather than 50 µA, and page program is 300 µs typical. The MX30LF2G18AC extends that to 2 Gbit and 4 Gbit on the same rail, with 50 µA maximum standby and 300 µs typical page program, so the driver carries across with a rail change.

The MX30LF1G28AD is a different generation and the difference is not cosmetic. It moves to a 2048 + 128 byte page on the smaller densities and a 4096 + 256 byte page at 4 Gbit, tightens ECC to 8-bit per 512 + 32 byte, drops endurance to 60K cycles and raises block erase to 4 ms typical. The MX30LF2G28AD and MX30LF4G28AD are the 2 Gbit and 4 Gbit members of that generation, sharing the 3 V rail and the larger page. They suit a host with a stronger ECC engine; they are the wrong direction when the host's ECC is fixed at 4 bits. Nothing between the two generations is a drop-in: the package footprint is the same, but the page size and the ECC depth are not, so the driver needs real work.

Where the part stops being the right answer

When the box runs hot. Plus 85 °C is the top of the grade. A logger in a metal enclosure under direct sun, with a cellular modem inside, sees internal temperatures well above ambient, and a part rated to 85 °C has nothing left. Change the thermal design or the part.

When the host cannot do 4-bit ECC. This is the most common way a NAND design fails quietly. Endurance and retention are both stated with 4-bit ECC per 512 + 16 byte in the same line (p. 6). An MCU with a 1-bit ECC unit, or firmware that skips ECC because the first board happened to read back clean, produces a logger that works on the bench and returns corrupted records after a season. If the ECC engine is not there, this part is not the answer, and neither is any other SLC NAND.

When the design needs a file system for free. There is no controller in this package. Bad block management, wear levelling, ECC and address mapping are host work, so a team that wants to call a write function and forget about it should look at managed storage.

When 528 megabytes is not enough. The array holds 4 Gbit plus spare, and a logger that keeps raw waveforms for months will outgrow it.

When the board is a 3.3 V board. The absolute maximum on VCC is 2.4 V (p. 68). Putting this part on a 3.3 V rail does not degrade it, it destroys it.

When the capacity budget assumed 4096 blocks. Between 4016 and 4096 blocks are guaranteed good (p. 78). Ignoring the 80-block worst case is fine for a log file and not fine for a fixed-size circular buffer with no slack.

Bring-up checklist

Eight items, in the order they bite.

1. Scan bad blocks before the first erase. Read the first byte of the first and second page in the spare area of every block, then keep the table. An erase can wipe the bad block marks, so scan first (p. 78).
2. Confirm the ECC engine and its sector size. Four bits per 528-byte sector, four sectors per page. Get the boundary wrong and the ECC will correct against the wrong input all day without complaining.
3. Check the rail at the package under worst-case load. The window is 1.7 to 1.95 V (p. 69). A rail that sags below the minimum during a transmit burst is the difference between a working logger and a return.
4. Measure the inrush. Staggered power-up current reaches 30 mA maximum with a 1 ms rise time (p. 69). If the flash is power-gated, that current lands on the same rail as the modem.
5. Time a page program. 320 µs typical, 600 µs maximum (p. 70). Firmware that waits a fixed 200 µs will eventually collide with a slow page, and the collision shows up as a missing record.
6. Pull up R/B# properly. The pin sinks 3 mA typical and 4 mA maximum at 0.2 V (p. 69), so size the pull-up against 4 mA.
7. Know what PT does at power-on. If PT is high when the device powers up, the whole chip is protected from program and erase even with WP# high, and an unprotect sequence has to run before the first write. PT low or floating disables the protection (p. 14).
8. Run one full wrap of the array. Write every page once, read it back, count the failures. It is the only test that exercises the bad block table, the ECC path and the address arithmetic together.

Frequently asked questions

Sourcing note

Tell us the annual volume, the rail voltage and the temperature the flash package will actually see, and we will quote the MX30UF4G18AC-XKI against the current datasheet revision, document PM2601 Rev. 1.0. Packing is confirmed with the part number, so say whether your line needs reel or tray. Ask for the lifecycle position and the PCN policy in the same reply; a logger product that ships for years needs that on paper. The same conversation can cover the 3 V members of the family and the 48-pin TSOP version.