An automotive event recorder in this build is a sealed unit behind the instrument panel that keeps a rolling log of vehicle states and freezes the final record when a trigger fires. The selection problem is that the trigger, the power cut and the write land on the same instant, the BOM has no room for a backup cell, and the box has to survive a cabin that swings from cold mornings to parked summer afternoons. Those constraints compress the memory choice into a very small block.
The part is a 64 K (8 K × 8) bit ferroelectric RAM (FeRAM) from RAMXEED organised as 8,192 words of 8 bits, on an I2C bus running to 1 MHz, from a 2.7 V to 3.6 V supply, in an 8-pin plastic SOP (p. 1). Three numbers decide the architecture. Writes complete with no wait time after the stop condition, so there is no polling and no window in which a record can be half finished (p. 4, p. 6). Endurance is 10^12 times per byte, so a rolling buffer can be rewritten all day without wear levelling (p. 1). And retention is specified with no battery attached: 10 years at 85 °C, 95 years at 55 °C, over 200 years at 35 °C (p. 1).
The verdict up front. For a cabin-mounted recorder on the 3.3 V rail, sharing the existing I2C bus at 400 kHz or 1 MHz, with event history measured in kilobytes, this is a clean fit. It stops being the right answer the moment any of four things is true: the rail is 1.8 V, the mount runs hotter than 85 °C, the design must claim automotive qualification, or the log grows past 64 Kbit. Section three covers each exit and its sibling.
The constraints that actually decide this
Six constraints do the selection work; none of them is capacity.
The record must land during the crash. The trigger and the loss of the vehicle rail are usually the same event. A memory with a fixed write window after the stop condition can be interrupted mid-cycle, and the last record is exactly the one that dies. This socket needs a part that finishes the write before the controller loses power.
No backup cell in the BOM. The sealed housing has no coin cell, no supercap and no second regulator. The memory must be nonvolatile on its own and hold data for the service life of the vehicle.
The bus already exists. The accelerometer, the ambient sensor and the MCU share one I2C line. A second bus means a second connector run and a new driver stack, so the memory must speak I2C at the speed the existing master drives, Fast Mode or Fast Mode Plus.
The footprint is fixed. The board was laid out around an 8-pin SOP, the part sits under a metal bracket, and the pad pattern is not changing for this component.
The ambient is the cabin. Cold soak on a winter morning and a parked car in summer sun set the two ends of the range. The memory must be specified across both, or the placement has to change.
The budget is tight. The memory should be the smallest part that satisfies the other five constraints.
Battery-backed SRAM fails the second constraint. EEPROM fails the first, because every write owns a wait window. NOR flash fails both the first and, over the life of the buffer, the endurance picture. What survives is ferroelectric memory in a small package, on a bus the board already speaks.
Mapping each constraint to a datasheet number
| Constraint | Datasheet number | Source |
|---|---|---|
| Record must survive the power cut | Write completes with no programming wait after the stop condition; no ACK polling required | p. 4, p. 6 |
| No backup cell | Retention without a battery: 10 years at 85 °C, 95 years at 55 °C, over 200 years at 35 °C | p. 1 |
| Existing I2C bus | 1 MHz maximum clock; Fast Mode Plus entry at 1000 kHz | p. 1, p. 11 |
| Rail | 2.7 V to 3.6 V recommended; absolute maximum from 0.5 V below ground to 4.0 V | p. 10 |
| Cabin ambient | Operating ambient 40 below zero to 85; storage 55 below zero to 125, both in °C | p. 1, p. 10 |
| Fixed footprint | 8-pin plastic SOP 150mil; 3.90 mm × 4.90 mm body; 1.75 mm maximum mounting height; 1.27 mm lead pitch | p. 16 |
| Continuous rewriting | Endurance 10^12 times per byte | p. 1, p. 13 |
| Power budget | 250 µA typical at 1 MHz (375 µA maximum); 100 µA typical at 400 kHz; standby 5 µA typical, 20 µA maximum | p. 1, p. 11 |
Four rows deserve commentary.
The first row is the architectural one. Because the cell is ferroelectric, data lands in the array as soon as the acknowledge finishes (p. 7). There is no internal page buffer draining on its own clock after the stop condition, which is where EEPROM writes get lost. If the rail dies mid-byte, the interruption lands at a byte boundary and the record checksum catches it, a detectable failure rather than a silently torn write.
A circular buffer that rewrites its whole 8 Kbyte span continuously never approaches the per-byte limit, so the driver needs no wear levelling or block rotation. The pointer simply advances and wraps, which the page write does naturally at the top of the array (p. 7).
At the full 1 MHz bus the part draws 250 µA typical; at the 400 kHz the master actually runs during steady logging it draws 100 µA typical (p. 11). Standby is 5 µA typical (p. 11). On the 3.3 V rail that is under a milliwatt while recording, inside the always-on power budget vehicle architects hand out for wake-source peripherals.
The retention row is temperature-dependent in exactly the way a parked car is: 10 years at 85 °C, 95 years at 55 °C, over 200 years at 35 °C (p. 1). A frozen event record sits untouched after the trigger, so the question is how hot the box gets while parked. In a cabin installation out of direct sun the guarantee is far beyond the service life of the vehicle, and the same row says this record belongs in the cabin, not on the windshield.
Where the part stops being the right answer
Rail below 2.7 V. The recommended supply window starts at 2.7 V (p. 10), and no level shifting fixes a supply below the memory's floor. There is also a power-down rule: if VDD ever falls below 2.0 V, the next power-up must start from 0 V or the device may misbehave (p. 13). A rail that sags and recovers without a clean restart violates that rule by design.
Heat beyond the cabin. Operating range runs from 40 below zero to 85 °C (p. 1). A unit on top of the dashboard in a sun-soaked market will see surface temperatures past that, and the datasheet makes no AEC-Q100 claim anywhere. For an engine bay or windshield-top installation this is the wrong answer regardless of the electrical numbers, and that decision belongs at stage one, not in a thermal chamber later.
More than 64 Kbit of history.
The organisation is 8,192 words of 8 bits (p. 1). If the log grows to include image indices or several sensor channels, the density ceiling arrives quickly, and the family provides the exits without leaving the vendor.
Bus faster than 1 MHz. The AC table tops out at Fast Mode Plus (p. 11). If the platform moves the recorder onto SPI, the same silicon story exists across the family with different interfaces.
The family map, each checked against its own datasheet: MB85RS64 holds the same 64 Kbit on SPI at up to 20 MHz from the same 2.7 V to 3.6 V window, drawing 1.5 mA typical at full clock, the drop-in when the board moves to SPI. MB85RS64T stays at 64 Kbit and 10 MHz but widens the supply to 1.7 V to 3.6 V, lifts endurance to 10^13 times per byte and quotes retention as 40.2 years at 85 °C, a visibly different trade than this part's 10 years. MB85RS128B doubles the density to 128 Kbit at 33 MHz (25 MHz on READ) from 2.7 V to 3.6 V with 9 µA typical standby. MB85RS1MT jumps to 1 Mbit in a wafer-level package at 30 MHz (40 MHz with the fast-read command) from 1.7 V to 3.6 V, sleeping at 10 µA maximum. MB85RS4MT reaches 4 Mbit in a 208mil SOP at 40 MHz from 1.8 V to 3.6 V with 10^14 cycles per byte. At the small end, MB85RS16 is the 16 Kbit sibling for variants that record almost nothing, and MB85RS16N teaches the most about heat: its range extends to +95 °C and it quotes endurance by temperature, 10^10 per byte at 95 °C against 10^12 at 85 °C, the family being explicit that heat costs cycles. Where the recorder streams camera metadata, MB85RQ4ML moves to quad SPI at 108 MHz and 54 MB/s.
Bring-up checklist
- Strap A0, A1 and A2 to VDD or VSS. They are internally pulled down, so a floating part answers at address 000, and up to eight of these share one bus (p. 2). Keep them at a fixed level for the whole transaction (p. 13).
- Pull SDA up properly. It is open drain, and the output specification is 0.4 V maximum at 3 mA sink (p. 11); size the pull-up for the bus length, not the bench. For ESD the part is qualified to 2000 V HBM, 200 V MM and 1000 V CDM with 200 V latch-up immunity (p. 14), but lines that leave the board still want their usual TVS.
- Decide WP on purpose. High protects the entire array, low or floating enables writes, and reading works either way (p. 2, p. 6). A recorder that freezes records on trigger wants a GPIO here so service mode can lock the log.
- Check host levels. VIH is 0.8 times VDD and VIL is 0.6 V maximum (p. 11), so a 3.3 V master is fine and a 1.8 V master is not.
- Respect the power-down contract in firmware: brownouts that dip below 2.0 V must be treated as a full power cycle, and the supply rise time belongs above 10 µs with 85 ns level hold times around the transitions (p. 13).
- Keep the software reset sequence in the driver: nine repetitions of a start condition with a data one, sent before a command after any bus fault (p. 9).
- Program the part after reflow. Data written before reflow is not guaranteed (p. 13), and the package is Moisture Sensitivity Level 3 (p. 14).
- Order the packing that the line accepts: the AME2 code ships in a tray, the AMERE2 code on embossed carrier tape at 1,500 pieces per reel (p. 15).
Frequently asked questions
Can it replace a standard I2C EEPROM in the same footprint?
Electrically yes at the bus level: the device address word uses the same 1010 type code with three address bits and a read/write bit (p. 5). The acknowledge polling that EEPROM code needs can be deleted outright (p. 6). The one behavioural difference is the page write, which wraps at the top of the array rather than at a page boundary (p. 7).
What happens if the rail browns out but does not die?
If VDD dips below 2.0 V and recovers, the device has not re-initialised, and the datasheet requires a restart from 0 V in that situation (p. 13). A supervisor that forces a clean reset, or a rail that collapses fully, keeps the memory in a defined state. A sagging rail hovering in the middle is the failure this rule exists to prevent.
How many recorders or other devices can share the bus?
Up to eight of these memories, selected by the A2 A1 A0 pins (p. 2). The bus also carries sensors, and the 1 MHz ceiling (p. 11) applies to the whole bus, so the clock must satisfy the slowest device.
Is the tray version different from the tape version?
No. The silicon is identical; AME2 ships in a tray, AMERE2 on embossed tape at 1,500 pieces per reel, tray minimum on request (p. 15). Pick by what the placement machine handles.
Sourcing note
The MB85RC64A is RAMXEED silicon; the company was previously Fujitsu Semiconductor Memory Solutions and keeps the part numbers unchanged (p. 1). The part is lead-free and meets RoHS, REACH and China RoHS (p. 14). Standard packing is 1,500 pieces per reel, 9,000 per outer box, or trays of 476 pieces (p. 18, p. 22). Send us your annual quantity and packing preference, and we will quote the tray and tape codes, the wider RAMXEED FRAM family and long-term availability for the suffix you freeze.