An automotive event recorder is a sealed box behind the dashboard that keeps a rolling window of sensor and camera events and freezes it when something happens. The hard part is that the trigger and the power loss are usually the same event: the recorder has to finish a write in the same instant that the crash takes the rail away.
This build uses the MB85RC512TPNF-G-AME2, an I2C FRAM from RAMXEED organised as 65,536 words of 8 bits, running from 1.7 V to 3.6 V with a 3.4 MHz bus in High Speed Mode and an endurance of 10^13 times per byte (p. 1). It is here rather than an EEPROM for one line in the datasheet: the part needs no programming wait after the stop condition (p. 4). No write window, so no half-finished record to come back to.
The short answer is that for a recorder in the cabin, on the MCU rail, rewriting a rolling buffer all day, this is a clean fit. It is not the right answer for a module in the engine bay or on top of the dashboard, because the datasheet stops at 85 °C and makes no AEC-Q100 claim anywhere. That is a stage 1 decision, not a discovery in the thermal chamber.
Stage 1 Defining the electrical envelope
Three things set the envelope before anyone looks at a part number: how much history has to survive, how the rail dies, and how hot the box gets. The bus is the easy part, because the accelerometer, the temperature sensor and the MCU already share one I2C line, so reusing it costs two pins and no new driver stack.
History. The unit that matters is the event record, not the raw sensor stream. A record here is a timestamp, a few channel values, a state word and a checksum, so a window of a few thousand records fits inside 64 Kbytes (p. 7). That is what makes a serial memory viable: no file system, just a circular buffer and a write pointer.
The rail. The recorder shares the rail with the MCU, fed from the vehicle bus through a buck. When the crash relay opens, that rail falls in milliseconds and no shutdown routine runs in time. Any memory whose write has to complete after the MCU has gone is the wrong memory here.
Heat. The box sits behind the dashboard, so the ambient is the cabin, and a dashboard top in direct sun is past the top of this part's range. Mounting location is part of the envelope, not a mechanical afterthought.
| Parameter | Datasheet value | Source |
|---|---|---|
| Density and organisation | 65,536 words × 8 bits | p. 1 |
| Supply voltage | 1.7 V to 3.6 V | p. 13 |
| Bus clock | 3.4 MHz maximum in High Speed Mode | p. 15 |
| Write cycle time | none, no polling after the stop condition | p. 4 |
| Endurance | 10^13 times per byte | p. 17 |
| Data retention | 10 years at 85 °C, 95 years at 55 °C | p. 17 |
| Operating current at 3.4 MHz | 0.71 mA typical, 1.2 mA maximum | p. 14 |
| Standby current | 15 µA typical, 120 µA maximum | p. 14 |
| Sleep current | 4 µA typical, 10 µA maximum | p. 14 |
| Temperature range | -40 to +85 °C | p. 13 |
| Package | 8-pin plastic SOP 150mil | p. 1 |
Two rows deserve a second look. Endurance is not the constraint: a recorder that rewrites the whole buffer every second for the life of the vehicle will not approach 10^13 cycles per byte, which is the point of using FRAM instead of wear-levelling an EEPROM. Retention is the constraint. The datasheet guarantees 10 years at 85 °C, and a rolling buffer renews every cell it touches, so data stays fresh while recording continues.
The temperature row decides where the box may be mounted. The grade is -40 to +85 °C, and the absolute maximum table allows the same range for operation (p. 13). With no automotive qualification statement in the document, the design earns its margin by placement.
Stage 2 Picking the part and reading the datasheet
The ordering code decodes into things a purchase order and a placement machine both care about. The datasheet lists four codes and the silicon is the same in all of them: the JNE1 code ships in a tube, JNERE1 and AMERE2 ship on embossed carrier tape at 1,500 pieces per reel, and AME2 ships in a tray with the minimum quantity on request (p. 19). The tail of the code is a packing decision, so confirm with the line whether it can take a tray at all.
On the bus, the device address word is fixed: 1010 followed by three address bits from the A2, A1 and A0 pins and one read/write bit (p. 5). Those pins are pulled down internally, so a part with all three open answers at address 000 (p. 2). Up to eight of these can share one bus (p. 2), which matters when one recorder design is reused across vehicle variants and each wants its own memory.
Access is a two byte address followed by data (p. 6). That changes the driver: the page write wraps at the top of the array rather than at a page boundary, so a buffer that runs off the end continues from address zero instead of corrupting the start of the same page (p. 7).
High Speed Mode is where the bus stops being trivial. Reaching 3.4 MHz requires the master to send the entry code 0000 1XXX after a start condition, accept a NACK from the slave, and only then switch its own timing (p. 9). Many automotive MCUs stop at 1 MHz Fast Mode Plus, which the same AC table covers, so 3.4 MHz is a ceiling on the part rather than a promise about the host (p. 15).
One trap fails as a mysterious hang instead of an error. The reserved slave ID F8h appears twice: with 86h it puts the device into sleep mode, and with F9h it reads the 3-byte device ID (p. 10, p. 11). Firmware that sends the wrong second byte either reads nothing or puts the memory to sleep mid-session.
If the design changes after the first board, the family covers the axis that usually moves first. MB85RS64T keeps 64 Kbit on SPI at 10 MHz from 1.7 V to 3.6 V with 10^13 cycles per byte. MB85RS1MT moves up to 1 Mbit at 30 MHz on 2.7 V to 3.6 V, and MB85RS4MT goes to 4 Mbit at 40 MHz from 1.8 V to 3.6 V with 10^14 cycles. Where the record rate is the real problem, MB85RQ4ML moves to quad SPI at 108 MHz and 54 MB/s on a 1.7 V to 1.95 V rail. The one that teaches the most about grade is MB85RS16N, which quotes endurance per temperature: 10^10 at 95 °C and 10^12 at 85 °C. That is the same silicon behaviour this part hides behind a single headline number.
Stage 3 Layout and bring-up traps
The write protect pin protects nothing by default. WP is pulled down internally to VSS, so an open pin means the whole array is writable (p. 2). Reading is allowed either way (p. 6). A recorder that must keep one block inviolable has to drive WP high from a GPIO and hold it there for the whole access, because the datasheet asks for WP and the address pins to stay fixed from start to stop (p. 18).
Three devices at address zero. With A0, A1 and A2 pulled down internally, three boards built without straps all answer to the same address (p. 2). Strap them on the board.
The power ramp has a floor, not just a ceiling. The supply has to rise more slowly than 0.05 ms/V, and the bus has to be held above VDD × 0.7 for 250 µs while the part comes up (p. 17). On the way down the requirement flips: SDA and SCL must stay above VDD × 0.7 for at least 85 ns after the rail starts to fall (p. 17). A crash cuts the rail far faster than that, so this decides whether the last transaction counts as complete.
Wake-up is not free. Sleep mode drops the current to 4 µA typical, but leaving it costs up to 400 µs of internal regulator recovery before the first command is accepted (p. 10, p. 14, p. 17). A recorder that sleeps between events has to add that delay to its trigger latency, and it cannot trust the address counter after power-up either, because that counter holds no valid value until the first write or read sets it (p. 8).
Stage 4 What carries into production
The first production issue is packing, not silicon. AME2 arrives in a tray and its minimum quantity is quoted on request rather than fixed (p. 19). A line that only accepts reels has to order AMERE2, the same part on embossed carrier tape at 1,500 pieces, or the first build stops at the loader.
The second is programming order. The datasheet states that data written before reflow is not guaranteed and recommends programming after reflow (p. 18). For a recorder that ships with a serial number and a calibration block already in memory, the programming step belongs at the end of the line.
The third is traceability with two hooks. The marking carries the environmental code plus a year and week code, so a lot can be read off the body in failure analysis without the reel label (p. 21). The device ID command returns three bytes with manufacturer ID 00Ah and product ID 658h, a cheap end-of-line check that the right density went into the right housing (p. 11).
The fourth is moisture and handling. The part is MSL 3, so floor life and bake rules apply once the bag is open, and ESD is rated at 2000 V HBM and 1000 V CDM (p. 18).
The fifth is geometry: a 3.90 mm by 4.90 mm body on a 1.27 mm pitch with a maximum mounted height of 1.75 mm (p. 20). The height matters in a housing drawn around another package.
Frequently asked questions
How long does a first article take?
The lead time question is mostly a packing question. The part ships unprogrammed, in a tray under the AME2 code or on tape under AMERE2, and the tray minimum is quoted per order (p. 19). Keep programming in-house so the first article does not wait on a factory queue.
Which layout mistakes show up most often?
Three. WP left floating, which leaves the array writable (p. 2). A0, A1 and A2 left floating, which puts every board at the same address (p. 2). And a pull-up sized for a 100 kHz bus carried onto a 3.4 MHz one, where the AC table assumes a 100 pF load (p. 15).
Does the part stay consistent from unit to unit?
Endurance, retention and the AC limits are qualification values, not per-unit screens, which is normal for this class. What can be checked per unit is identity and function: the device ID returns 00Ah and 658h (p. 11), and the marking carries a year and week code (p. 21).
What can replace it if the design changes?
Down in density and onto SPI, MB85RS64T is 64 Kbit at 10 MHz from 1.7 V to 3.6 V. Up in density, MB85RS1MT is 1 Mbit at 30 MHz and MB85RS4MT is 4 Mbit at 40 MHz with 10^14 cycles. MB85RS128B sits in between at 128 Kbit, with 33 MHz for all commands except READ. For bandwidth, MB85RQ4ML is quad SPI at 108 MHz and 54 MB/s, though its supply is 1.7 V to 1.95 V rather than 3.3 V. If the temperature grade is what changes, MB85RS16N publishes endurance per temperature, 10^10 at 95 °C and 10^12 at 85 °C.
Migration from an EEPROM is a driver change rather than a board change. The pins are A0 to A2, VSS, SDA, SCL, WP and VDD (p. 2), so an existing footprint in this class usually carries over. What changes is the address, now two bytes, and the completion rule, which is an acknowledge rather than a status poll (p. 6, p. 7).
Sourcing note
Send the record size, the rail, the mounting location and the annual quantity, and we will quote the MB85RC512TPNF-G-AME2 against datasheet DS501-00028-6v1-E with the packing code confirmed on the order. The datasheet carries no lifecycle or PCN commitment, so ask for a longevity statement for this grade with the quote. If the module may end up outside the cabin, say so at quotation stage.