A drone's timing tree is tighter than its size suggests. One TCXO feeds the GNSS receiver, the flight controller and the radio link — and every split of that clock is a chance to add jitter that shows up later as degraded positioning or a flaky video link. The INS6102B from DAPU (Dapu Tunwei) is a 1-to-2 low-additive-jitter clock buffer made for exactly this fan-out, in a package smaller than the crystal it serves.
The short answer
When one master clock — typically a TCXO — must drive two loads with essentially no added jitter, in a battery-powered device where every square millimetre counts, the INS6102B is the straightforward answer: 0.35 ps LVCMOS added jitter, 0.8 × 1.6 mm WCSP package, level-shifting built in.
Verified key parameters
From the INS6102B V1.1 datasheet (Guangdong DAPU):
| Parameter | Value | Condition / Note |
|---|---|---|
| Configuration | 1:2 clock fan-out buffer | Dual-channel, CLK_REQ1/CLK_REQ2 |
| Output type | 2 × LVCMOS | 10 – 80 MHz |
| Added jitter (LVCMOS in) | 0.35 ps typ | 26 MHz, 0.8 Vpp, 10 Hz – 5 MHz BW |
| Added jitter (sine in) | 0.40 ps typ | 26 MHz, 1.4 Vpp, 10 Hz – 5 MHz BW |
| Input support | Sine and square wave | Min 0.3 Vpp sine; internal AC coupling |
| Output edge control | Adaptive slew limiting | Reduces EMI |
| Level shifting | High/low level conversion | Input-to-output domain |
| Integrated LDO | 1.8 V output | Powers the output stage cleanly |
| Package | WCSP-8 (0.4 mm pitch), 0.8 × 1.6 mm | |
| Temperature | −40 to +85 °C | |
| Compliance | RoHS |
Why the drone case keeps landing on this part
One TCXO, two masters. The GNSS receiver wants a clean 26 MHz reference; the flight MCU or radio SoC wants the same frequency on its own pin. Cutting the trace into two with a plain splitter couples the loads and adds reflections. A buffer regenerates each output and isolates the loads — and the INS6102B does it with less than half a picosecond of added jitter, which is below the noise floor concern for any consumer GNSS chain.
CLK_REQ pins match the power-domain reality. Phones and drones power domains up and down aggressively. The two clock-request inputs let each downstream block gate its own clock leg independently — the GNSS can sleep while the radio keeps its reference, and vice versa.
The 0.8 × 1.6 mm footprint. A typical 2016 TCXO occupies 2.0 × 1.6 mm. The buffer adds fan-out capability in less area than the source itself — the reason it shows up in handset-class designs and migrates naturally into compact flight controllers.
Built-in level shifting and AC coupling. A 1.8 V TCXO feeding a 3.3 V radio, or a clipped sine feeding an LVCMOS input — these mismatches are exactly what the internal AC coupling and level-conversion stage absorb without external translators.
The EMI detail most buffers ignore
Fast output edges radiate. The INS6102B's adaptive output stage limits output slew rate — trading a fraction of an edge for a cut in harmonics. In a drone, where the GNSS antenna sits metres of flight-controller wiring away from a video transmitter, gentler clock edges on the distribution tree are free EMI margin.
Where it fits and where it does not
Good fit:
- GNSS receivers sharing a TCXO with an MCU or radio
- Smartphone, GPS, WLAN, FM, W-BT clock trees (the datasheet's named applications)
- Portable radios and drones where size and jitter both matter
Wrong fit:
- More than two outputs — look at 1:4 or 1:6 fan-out buffers
- Differential output domains (LVDS/LVPECL) — this is an LVCMOS part
- Clock generation — this buffers, it does not synthesise
Frequently asked questions
What jitter can I expect end to end?
The buffer adds 0.35 ps RMS (LVCMOS input, 26 MHz, integrated 10 Hz–5 MHz). Total chain jitter is dominated by your TCXO's phase noise; the buffer's contribution is essentially invisible next to a typical TCXO.
Can the inputs take a clipped sine from a TCXO?
Yes — sine input is supported down to 0.3 Vpp with internal AC coupling, which is the standard clipped-sine TCXO case. No external bias network required.
How do the two outputs turn on and off?
Each output is gated by its own clock request input, CLK_REQ1 or CLK_REQ2. Assert the request and that leg runs; deassert it and the leg stops independently.
Does it need a clean supply?
The part includes an internal 1.8 V LDO for its output stage, which isolates the output swing from supply noise to a useful degree. Standard decoupling per the datasheet application circuit is sufficient.
Sourcing note
The INS6102B ships through Mandu with the V1.1 datasheet and application notes. Send your TCXO frequency and load count for a quotation, including tape-and-reel options for production.