An edge AI vision module lives or dies on one number: how fast the working memory can absorb a frame while the neural engine chews through the last one. Two memory routes are in production for that job, and both work. Route A hangs an octal DDR pseudo-SRAM like the CSS6408LQ-L on the host and lets the wide double-data-rate bus swallow frame data. Route B keeps the familiar quad SPI controller and accepts the narrower pipe. Neither part asks the host to manage DRAM refresh; both are 64 Mb, both organize as 8M x 8, and both run the industrial temperature range as standard.
The CSS6408LQ-L is the Route A part. It speaks octal SPI in DDR mode, moving two bytes per clock cycle at clock rates up to 133 MHz, which the datasheet states directly as 266 MB/s read/write throughput (p. 3). Supply is a single rail class, 2.7 to 3.6 V on both VDD and VDDQ, and the part arrives in a QFN body under the LQ ordering suffix (p. 3, p. 5). The Route B counterpart from the same vendor is the CSS6404L family, a quad SPI pseudo-SRAM in SOP-8 or USON-8 with the same density, the same organization and the same self-managed refresh (its datasheet).
Short version: pick Route A when the pipeline streams continuously and the frame buffer is the bottleneck, pick Route B when the board is pin-starved, the microcontroller only speaks quad SPI, or the memory mostly holds small per-frame scratch regions rather than a moving pixel stream. If your frames already fit a 109 MHz quad bus with margin, you can stop reading and take Route B.
Route A in practice
Route A is a ten-pin conversation. The signal set is CE#, CLK, RESET# and the eight-bit A/DQ bus shared between command, address and data, plus DQS/DM, data strobe on reads and data mask on writes (p. 6). After CE# drops, the instruction code latches on the first rising clock edge and the access address follows over the next four clock edges (p. 9). Memory accesses start on even addresses, a rule the driver enforces once and then forgets (p. 9).
Latency is where first-time users should read the datasheet twice. The default read latency count is 5 at 133 MHz, and the device powers up in variable latency mode: when an internal refresh lands inside a read burst, output data can be pushed out to as much as twice the programmed latency, while a fixed-latency mode exists for hosts that prefer a stable number over variance (p. 14, p. 10). Write latency defaults to 5 as well, and register writes always take one latency cycle (p. 14, p. 16).
Refresh is the part you never write code for. The array refreshes itself, and the knobs are all about power rather than correctness: Partial Array Self-Refresh limits refresh to the full array, half, quarter, or eighth of it, and Auto Temperature Compensated Self-Refresh uses a built-in temperature sensor to pace the refresh rate (p. 3, p. 16). The payoff shows up in the standby table. Full-array standby is 250 µA maximum at 85 °C and 350 µA maximum at 105 °C, with a typical figure of 100 µA, and trimming the refreshed region pulls the typical mean down to 80 µA at 25 °C for one-eighth coverage (p. 3, p. 19, p. 20). Unlike flash, neither route quotes a write-cycle endurance or a retention figure in years; data survives as long as the supply and the self-managed refresh do.
Active current is stated conservatively: 3 mA maximum at a 13 MHz clock and 14 mA maximum at 133 MHz, characterized rather than production-tested, so leave margin in the supply budget (p. 19).
Burst behavior matches what a display or camera pipeline wants. The part powers up in Hybrid Wrap 32 mode, wrap lengths of 16, 32, 64 or 1024 bytes are register configurable, and a Linear Burst command rides straight through the 1024-byte page; Row Boundary Crossing lets linear reads continue into the next row, though RBX writes are not supported (p. 3, p. 9, p. 17). Writes have a two-byte minimum, single-byte writes happen by masking with DM, and CE# low pulse width tops out at 8 µs on the standard grade and 3 µs on the extended grade, so long bursts are chained with 18 ns CE# high gaps (p. 12, p. 21).
Two housekeeping items complete the route. Power-up takes 150 µs of self-initialization before Phase 2, the RESET# pad is optional because it carries an internal weak pull-up, and the board needs one low-ESR 1 µF capacitor close to VDD with an optional 0.1 µF for high-frequency transients (p. 7, p. 18, p. 21). Output drive strength is programmable across 50, 100, 200 and 400 ohm settings, with 100 ohm as the default (p. 15).
Route B in practice
Route B is the same idea wearing a smaller shoe. The CSS6404L is a quad SPI pseudo-SRAM with four SDR I/O pins, operating in SPI or QPI mode, in an 8-lead SOP or an 8-lead USON measuring 3 x 2 mm (its datasheet). Clock capability depends on how you burst: 133 MHz for 32-byte wrapped burst operation when the supply sits at 3.0 V plus or minus 10 percent, 109 MHz at 3.3 V plus or minus 10 percent, and 84 MHz for linear burst operation that crosses the 1 K page boundary (its datasheet). Active current is 7 mA maximum under half bus toggling, and standby holds the same 250 µA ceiling at 85 °C as the octal device (its datasheet).
Controller work is familiar to anyone who has driven a quad SPI flash: every read and write terminates by raising CE#, which the datasheet flags as mandatory because an unterminated command blocks internal refresh and corrupts memory (its datasheet). Power-up needs 150 µs plus an explicit device reset before the first valid command (its datasheet).
Where Route B quietly wins is the low-power branch. The CSS6404S family drops the supply to 1.62 to 1.98 V and caps the clock at 84 MHz. Ordered as CSS6404SS-L in SOP-8 and CSS6404SU-L in USON, it cuts the Ultra Low Power Halfsleep mode to 20 µA typical with data retained at 25 °C, against 100 µA for the 3 V CSS6404L family, with standby maximums of 200 µA at 85 °C (its datasheet). One packaging footnote matters for outdoor enclosures: the extended industrial USON option only reaches down to minus 25 °C, while the SOP-8 body covers the full minus 40 °C floor (its datasheet).
Head to head on the numbers
| Item | Route A, CSS6408LQ-L | Route B, CSS6404L family |
|---|---|---|
| Interface | Octal SPI, DDR | SPI/QPI, SDR |
| Bus width | 8-bit A/DQ, two bytes per clock | 4 SDR I/O pins |
| Stated throughput | 266 MB/s read/write | not quoted as a byte rate; clock rates are |
| Clock, wrapped burst | up to 133 MHz | 133 MHz at 3.0 V plus or minus 10%, 109 MHz at 3.3 V plus or minus 10% |
| Linear burst | through the 1024-byte page, RBX reads supported | 84 MHz, crosses page boundary |
| Density and organization | 64 Mb, 8M x 8, 1024-byte page | 64 Mb, 8M x 8, 1024-byte page |
| Supply | 2.7 to 3.6 V on VDD and VDDQ | 2.7 to 3.6 V; 1.62 to 1.98 V on the CSS6404S branch |
| Active current, max | 14 mA at 133 MHz (characterized) | 7 mA (characterized) |
| Standby, 85 °C max | 250 µA | 250 µA; 200 µA on the 1.8 V branch |
| Read latency | code 5 default, variable pushout to LC x 2 | output valid 5.5 ns max after clock |
| Burst length ceiling | CE# low 8 µs standard, 3 µs extended | CE# low 8 µs standard, 3 µs extended |
| Packages | QFN; 24-ball mini-FBGA on the LB suffix | SOP-8; USON-8, 3 x 2 mm |
| Temperature grades | minus 40 to plus 85, minus 40 to plus 105 °C | minus 40 to plus 85, minus 40 to plus 105 °C |
| Host refresh work | none | none |
Two rows decide most projects. The first is throughput: the octal datasheet states 266 MB/s flat out, while the quad datasheet quotes clock rates per burst mode and leaves the byte rate as arithmetic for the reader, which is itself a hint about what each part is for. A camera module pushing continuous frames feels the difference immediately; a display buffer never will. The second is capture complexity: DDR on eight pins means sampling against DQS with a variable latency pushout during refresh, while quad SDR at 109 MHz samples on a clock edge every team has debugged before (p. 10, p. 14).
How to decide for your build
- Where is the bottleneck? If the module streams frames continuously while the inference engine runs, the stated 266 MB/s is the number that matters. If memory traffic is short bursts between quiet periods, the quad part's wrapped bursts fit comfortably and its driver is already in your SDK.
- What does the host controller speak? An octal DDR interface needs a peripheral that generates DDR clocks and captures against DQS. If the chosen microcontroller only offers quad SPI, the decision is made by the silicon you already own.
- What happens between frames? Both routes leave refresh entirely on-chip, but the octal part exposes PASR, so a host that only touches the top eighth of the array can cut typical standby current from 100 µA to 80 µA at 25 °C (p. 20), and the low-voltage CSS6404S branch halves that again for battery-backed designs.
- Who assembles the board? The QFN body suits reflow lines; the SOP-8 and USON-8 bodies on Route B are friendlier to hand rework. When board area on Route A is tight, the same octal die is available as the CSS6408LB-L in a 24-ball mini-FBGA measuring 6 x 8 x 1.2 mm (p. 4).
Grade selection runs through ordering suffixes on both routes. The CSS6404LS-L is the commercial-grade SOP-8 part, the CSS6404LS-LI carries the minus 40 to plus 85 °C industrial range, the CSS6404LS-LJ extends to plus 105 °C, and the USON CSS6404LU-L mirrors the commercial and industrial options (its datasheet). On the octal side, the -LI suffixes are the 85 °C parts and the -LJ suffixes the 105 °C parts, in FBGA and QFN respectively (p. 5).
Frequently asked questions
How much does the board change when moving from quad to octal?
The octal part uses a ten-signal interface against roughly six on the quad route, adds a DQS/DM line and a second supply pin set, and the layout needs the close-in decoupling the datasheet calls for: a 1 µF low-ESR capacitor at VDD with an optional 0.1 µF nearby (p. 18). No external refresh circuitry or level shifters appear on either route.
Does the octal route add software work?
One driver of moderate depth. The command set is small and the burst engine is register configured, but the driver has to handle variable latency pushout during refresh or lock the latency mode at setup, and enforce the even-address and two-byte-write-minimum rules (p. 9, p. 12, p. 14). A quad SPI pseudo-SRAM typically reuses an existing flash-style driver with a wrap command added.
What does it cost to switch routes after layout?
On quad, switching between the 3 V and 1.8 V branches is a supply redesign, not a firmware one, since both branches speak the same protocol. Moving from quad to octal after tape-out is a new layout and a new driver, which is why the decision belongs in the schematic phase. Within the octal family the swap is lighter: the CSS6408LB-L and the QFN part share one specification table, so a footprint change does not touch the driver.
How stable is the supply situation on this family?
The octal and quad datasheets were released as branded versions in late 2022 and early 2023, and both ordering tables list a full temperature ladder across QFN, FBGA, SOP-8 and USON-8 bodies (p. 5). Availability and lifecycle status should be confirmed against current distributor stock at order time.
Sourcing note
The CSS6408LQ-L sits in the Cascadeteq 64 Mb octal DDR pseudo-SRAM family alongside the FBGA-packaged CSS6408LB-L, with -LI and -LJ suffixes marking the 85 °C and 105 °C grades. The quad SPI alternatives above cover the same density in SOP-8, USON-8 and a 1.8 V low-power branch. Tell us which route your frame budget points to, the grade your enclosure reaches and the annual volume, and we will quote against current stock.