A set-top box boots, reads a small block of state and hands it to the application: output resolution, the tuned channel list, the parental code, the DRM keys, the last firmware slot that booted. Get that block wrong and the box is not degraded. It is unusable in a way the subscriber notices within a minute.
Two routes for that block are in production. Route A puts it in a dedicated 32 Kbit serial EEPROM on the two-wire bus. Route B consolidates configuration, channel list and event log into a single 64 Kbit device. Both speak the same protocol at the same clock rate, so this is not an interface argument. It is an argument about how much of the box's state has to survive a power cut, and whether you want to spend a second device address later or pay for density now.
The 24LC32AT-I-SM is the Route A part: 32 Kbit organized as 4 K x 8, a 32-byte page write buffer, an SOIJ body and the industrial temperature range. Its Route B counterpart is the same family one density up, under the same SM and SN package codes. Short version: Route A is the better choice for a read-mostly map, and Route B when the box must keep a log the operator edits.
Route A in practice
Route A is one small device that the SoC owns completely. The map is a single block of 4 K x 8 bit, reached with the control byte 1010b followed by three chip-select bits and a read/write bit (p. 1, p. 7). Those three chip-select bits do double duty. They select the device on the bus, and they become the three most significant word address bits, which is how eight devices share one bus and appear as up to 256 Kbits of contiguous space (p. 7). Only A11 to A0 are used inside the part, so the same driver works whether one device is fitted or eight.
Writes are page-oriented. Data lands in a 32-byte buffer and is committed when the host issues a Stop condition, after which the write cycle is self-timed at 5 ms maximum and the device acknowledges nothing until it finishes (p. 1, p. 6, p. 8). Three consequences matter in a set-top box. A page write cannot cross a physical page boundary; if it tries, the pointer wraps to the start of the current page and overwrites what is already there. A write of fewer than 32 bytes still refreshes the whole page, so endurance is specified per page rather than per byte. And the WP pin protects the entire array when it is tied high, sampled at the Stop bit, so locking the configuration is a hardware decision rather than a firmware one (p. 8).
Pull WP high and the part still acknowledges a write command, but no write cycle occurs and nothing changes (p. 8). Firmware that assumes an acknowledge means success will report a save that never happened. That is the one behavior on this route worth a dedicated test.
The electrical side is unremarkable. The device runs from 2.5 V to 5.5 V at 400 kHz, draws 0.1 mA typical while writing and 0.01 µA typical on standby, and is specified past 200 years of retention and past 1,000,000 write cycles (p. 1, p. 2). On a set-top box duty cycle neither figure is the constraint. The one external component the bus needs is the pull-up on SDA, given by clock rate: 10 kΩ at 100 kHz and 2 kΩ at 400 kHz, with the same values on both routes (p. 5).
Where Route A earns its place is the read path. Boot reads are a few hundred bytes, they happen once per power-up, and 4 KB of map holds several hundred records of the size a settings block actually is. The device is also offered in DFN, MSOP, PDIP, SOIC, SOIJ, SOT-23, TDFN and TSSOP, and it is AEC-Q100 qualified (p. 1, p. 41).
Where it stops is growth. A channel list the operator edits, plus a rolling event log, plus two firmware slots of metadata, does not fit in 4 KB for long. Route A then compresses the log or adds a second device, and a second device costs another chip-select combination, another footprint and another driver instance on a bus the SoC already shares with a tuner and a PMIC.
Route B in practice
Route B is the same bus, the same page size and the same write cycle, with twice the map. The 64 Kbit device is a single block of 8 K x 8 bit. Its datasheet quotes the same page buffer, write cycle, endurance and retention.
| Route B parameter | Value | Where in the 64 Kbit datasheet |
|---|---|---|
| Organization | 8 K x 8 bit | Features |
| Supply range | 2.5 V to 5.5 V | Device selection table |
| Clock | 400 kHz | Device selection table |
| Page write buffer | 32 bytes | Features |
| Write cycle time | 5 ms maximum | AC characteristics |
| Endurance | 1,000,000 cycles | AC characteristics |
| Data retention | more than 200 years | Features |
| Operating current, write | 0.1 mA typical, 3 mA maximum | DC characteristics |
| Standby current | 0.01 µA typical, 1 µA maximum | DC characteristics |
| Control byte | 1010b plus three chip-select bits | Device addressing |
| Temperature ranges | I -40 to 85 °C, E -40 to 125 °C | Device selection table |
| Packages offered | MSOP, SOIC, SOIJ, TSSOP, PDIP, SOT-23, DFN, TDFN | Product identification system |
Every value in that table is taken from the 64 Kbit datasheet, document DS20001189U revision U. Nothing electrical changes on this route, so the migration is mostly arithmetic. What changes is the end address your driver checks against, and the room you gain for the parts of the box's state that used to be dropped.
One documentation trap is worth knowing before you write the power budget. The device selection table and the product identification system both state 2.5 V to 5.5 V for the 64 Kbit part, while the AC characteristics header of the same document lists the input voltage range as 1.7 V for both grades. The 1.7 V row belongs to the sibling devices in that datasheet, which are the ones specified down to that rail. Design against the device table and confirm the grade with the supplier.
Head to head on the numbers
| Item | Route A, 32 Kbit | Route B, 64 Kbit |
|---|---|---|
| Map | 4 K x 8 bit | 8 K x 8 bit |
| Address bits used | A11 to A0 | A11 to A0 in the same decode |
| Supply range | 2.5 V to 5.5 V | 2.5 V to 5.5 V |
| Clock at full rail | 400 kHz | 400 kHz |
| Page write buffer | 32 bytes | 32 bytes |
| Write cycle, self-timed | 5 ms maximum | 5 ms maximum |
| Endurance, per page | 1,000,000 cycles | 1,000,000 cycles |
| Retention | past 200 years | past 200 years |
| Write protect scope | whole array, sampled at Stop | whole array, sampled at Stop |
| Devices per bus | eight | eight |
| ESD protection, all pins | 4 kV minimum | 4 kV minimum |
| Standby current | 0.01 µA typical | 0.01 µA typical |
| Temperature grades | I and E | I and E |
| Automotive qualification | AEC-Q100 | by variant |
| Smallest package offered | TDFN | MSOP |
Two differences are worth pulling out. The first is throughput. Both routes commit 32 bytes per write cycle and both take up to 5 ms to do it, so neither is a candidate for streaming telemetry. A full rewrite of the Route A map is 128 page cycles at 5 ms each, a boot-time operation you schedule rather than something you do on every channel change. An application that appends a log entry per event saturates Route A first, and it saturates on page count rather than on bytes.
The second is that endurance is quoted per page, and a partial page write still costs a full page cycle. Both devices behave this way. A firmware that writes a two-byte flag to an otherwise untouched page is spending the same cycle as a full 32-byte update, and it is doing it to whichever page the two bytes land in. Route B does not fix that. It only buys you more pages to spread the wear across, which is a real benefit when the log is append-only and a real distraction when the problem is that the writer never buffers.
Power is not a differentiator at this scale: in a mains-powered set-top box, both parts are noise next to the tuner and the SoC (p. 2, p. 3).
How to decide for your build
Four questions.
- How much of the state is authoritative? If the box can rebuild the channel list from the network and only the subscription and the calibration have to survive, Route A is enough and 4 KB is generous. If the log has to survive a factory reset, Route B is cheaper than a second device.
- Is board area the constraint? Look at the packages before the densities. Route A's smallest option is a leadless TDFN and Route B is offered in MSOP, so density and area do not move together. A 64 Kbit part in MSOP can be a smaller placement than a 32 Kbit part in SOIJ.
- What temperature does the enclosure reach? Both routes offer the industrial grade at -40 to 85 °C and the extended grade at -40 to 125 °C (p. 41). A set-top box that shares a shelf with a power amplifier should be specified on the extended part, and the price difference is smaller than the cost of a field failure.
- Will the platform spawn variants? Route A carries AEC-Q100 qualification, which matters if the board is reused in a vehicle head unit. Route B is qualified by variant, so check which one your distributor holds.
Most of the traffic on this family is a package or grade swap rather than a change of route. The 24LC32A-SN is the same 32 Kbit die in the narrow 3.90 mm SOIC body instead of the 5.28 mm SOIJ body, and the 24LC32AT-SN is that part on tape and reel.
On the Route B side, the 24LC64-E-MS and 24LC64-I-MS are the 64 Kbit device in MSOP at the extended and industrial grades. The 24LC64-E-SM and 24LC64-I-SM are the same density in SOIJ at those grades, the 24LC64-E-SN is the narrow SOIC version, and the 24LC64-E-ST is the TSSOP version. All share the page size, write cycle and endurance of the part in this article.
Frequently asked questions
Can I drop the 64 Kbit device into the same footprint as this one?
If both are ordered under the SM package code, yes, they share the SOIJ body description of 5.28 mm and the same eight-lead two-wire interface. The change is in firmware rather than layout: the driver's end address and page count constants move.
Does a bigger EEPROM mean more software work?
Structurally, no. The control byte, the page boundary rule, the write cycle and the write-protect behavior are the same on both devices, so a driver written for one works on the other. The real work is in deciding what now lives in the extra map, because that is where a log gets added and where write amplification starts.
Why does a small write still cost a full page cycle?
Because the array refreshes the whole page when the write cycle runs. Endurance is therefore quoted per page rather than per byte, and a two-byte update costs the same as a 32-byte update. Buffer your updates and write whole pages; that single change does more for service life than any density upgrade.
What is the difference between the industrial and extended grades?
The industrial grade is specified from -40 to 85 °C and the extended grade from -40 to 125 °C (p. 41). Bus behavior is the same, and the standby current maximum rises from 1 µA to 5 µA on the wider grade (p. 2). Pick the grade from the measured enclosure temperature, not the ambient specification of the room.
Sourcing note
The 24LC32AT-I-SM is the industrial-grade, tape and reel version in the SOIJ body, and the same family is available in MSOP, PDIP, SOIC, TSSOP and TDFN if your layout needs a different footprint (p. 41). Tell us which route you have chosen, the grade your enclosure reaches and the annual quantity, and we will quote from current stock against the revision of the datasheet in force at the time.